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DekatronPC

Silicon-free computer on vacuum and cold-cathode tubes with pure brainfuck instruction set

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Decatrons can do +1 and -1 operations by design, so they are best devices for brainfuck instruction set.

As a next generation of BrainfuckPC, DekatronPC should have next characteristics:
> 16 + 16 Instructions - which includes 8 native Brainfuck instructions w\o any optimizations as before
> 6-gidit IP counter;
> 3 digit data counter from 0 to 255;
> 17 dekatrons.
> Sub-miniature tubes.
> Harvard architecture;
> Up to 1MIPS (as A110 can do that) - hope that will achieve 250kIPS;
> ROM and RAM size - currently unknown;
> RAM device - ferrite core memory

Motivation

DekatronPC is next project after BrainfuckPC relay computer. 

I made some architectural mistakes in relay computer and want to create more clear an much more insane device.

Overview

Harvard architecture with separate memory for code and data

30000 8-bit cells.

Decimal data representation

Instruction Set

Main point - pure brainfuck. If BrainfuckPC have fully-functional 16-bit adder and can ADD/SUB any 8-bit of 16-bit CONST, DekatronPC due to dekatron feature can do only +1 and -1.

DekatronPC instructionbrainfuck equivalent description
INC+Old value from current memory cell is loaded into dekatron counter, incremented and stored back
DEC-Old value from current memory cell is loaded into dekatron counter, decremented and stored back
ADA>Increment number of current memory cell (go forward through memory)
ADS<Decrement number of current memory cell (go backward through memory)
IN,Read ASCII symbol from terminal and store it in a current memory cell
OUT.Write value from current memory cell to a terminal
[[If value of current memory cell is not zero - do nothing.
If zero - increment IP pointer while the end of this loop is not founded
]]if value of current memory cell is zero - do nothing
If not zero - decrement IP pointer while the begining of this loop is not founded.
NOPn/aUsed for loop alignment

Architecture

DekatronPC can be used in two modes:

  •  In clear lamp mode. Ferrite memory work in direct mode  - when program is loaded directly to instruction memory and data memory working without any external storage. No transistors are used in this mode, but we are limited with 3KB of instructions and 1.5Kb of data.
  • In insane mode. Ferrite memory works in cache mode and external storages are used for storing instructions and data. No size limitations, but outside lamp logic we can use transistors.

Hardware, which can support described instruction set can be implemented on four reversible dekatron counters:

  1.  IP counter - can count from 0 to 999999 (6 dekatrons). Just represent current instruction number
  2. Loop level counter - can count from 0 to 999 (3 dekatrons). Used for cycles limits lookup
  3. AP counter - can count from 0 to 29999 (30000 memory cells ) (5 dekatrons). Just represent current memory cell
  4. Data counter - can count from 0 to 255 (3 dekatrons). Used for loading data from memory, modifying it, printing, reading and storing in memory

Just only 17 dekatrons are needed to make the whole device. But each dekatron require up to 10 vacuum tubes. 

MullardBook2Part3ValvesJan1971.pdf

valves and tubes datasheet

Adobe Portable Document Format - 10.48 MB - 02/02/2018 at 09:24

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Adobe Portable Document Format - 1.08 MB - 02/02/2018 at 09:23

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Adobe Portable Document Format - 748.14 kB - 02/02/2018 at 09:23

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  • Experimental dekatron cell assembly

    Artem Kashkanov7 hours ago 0 comments

    I have a good assembly progress in experimental dekatron cell. All modules are already installed into 3U crate. Today I added connector holders - and now can start wiring it up. I also wait for new sockets to add them on unit 3.

  • Experimental dekatron cell get two more tube plates

    Artem Kashkanov2 days ago 0 comments

    I made two more tube plates for experimental dekatron cell. 

    From left to right

    • BCD-to-BIN coder unit
    • 6-channel voltage stabilizer unit
    • Dekatron unit with BIN-to-BCD coder and carry output
    • [Required to build] Write amplifiers and level shifters unit

    Now, 3U crate look like this. But I need to re-drill the rail holes to give the modules more space between each other. On the back, coolers, transformers and rectifiers would be added.

  • Experimental Dekatron cell became more real

    Artem Kashkanov02/21/2022 at 12:49 0 comments

    I start building process of experimental dekatron cell. The idea is to develop and debug Read and Write control circuits for dekatron.  All other computer stuff can be just created from regular logic elements, but not this one. Voltage difference is up to 900V, about 6 different voltages and cray amount of tubes.

    I selected 3D-wiring because need to develop schema first. So this unit is for debug purposes only. Further 17 dekatron unit would be PCB-based with subminiature tubes.

    This is how future 3U block will look like. Lately I'll add other modules, PSU, coolers and so on.

  • Experimental Dekatron Cell

    Artem Kashkanov02/17/2022 at 09:16 0 comments

    For my Dekatron-based vacuum tube computer I need to build 4 counters with 17 dekatrons with few deviations between counters:

    IP( Instruction Pointer) counter - generates address of current instruction. Has 6 dekatrons so can handle regions from 0 to 999999. Doesn't require any write operations but has full Reading block. Also set to 0 required

    LOOP Counter - Collect current loop level for loop lookup process. We can do IP++ or IP-- so need to scroll instruction chain like +++[+[+[+]++ with counting current level of skipped loop. Doesn't require any write or read operations. Set to 0 required and Zero output requested.

    AP (Address pointer) counter - contain 5 dekatrons and handle from 0 to 29999 cells - as Brainfuck has 30k cells.  Doesn't require full Write block but need set to 0 for all block and set to 2 for highest dekatron. Full read block.

    Data counter - contain 3 dekatrons and handle from 0 to 255. It require full write block, full read block and block with will do 0 to 255 and 255 to 0 operations carefully. So first I want to build full noval-based dekatron cell like rendered one.

    This is a cell circuit without write logic. 

    Dekatron PCB would be look like this (but I need to update all renders as already modified the circuit).

  • Vacuum tube computer emulator: hardware

    Artem Kashkanov06/07/2021 at 08:20 0 comments

    Main milestone is almost done.  FPGA-based emulator became more real as before.

    The idea of making emulator is to develop whole logic-level architecture of the future vacuum tube computer on Verilog.

    Initially we have nothing to check the idea, but with the first physical emulation block we can "build" the computer schema, test it, debug it, improve it and we would get fully-functional computer, which can perform brainfuck programs.

    After this milestone would be done, we can start assembling any computer block as physical parts. e.g. - build IP counter or opcode decoder and so on. This physical block would replace emulated parts and we would get fully functional computer again.

    With replacing other emulated blocks with the physical finally we could remove emulator and would get fully functional fully-built vacuum tube computer.

    Currently, emulator contain DE0 nano Soc dev board, demux I\O board for indicator part and text display, nixie display for counters and a keyboard. Further, some high-speed I\O boards would be added.

  • DekatronPC insights: Verilog model develop

    Artem Kashkanov04/22/2020 at 08:12 0 comments

    I started develop the Verilog model of DekatronPC computer in order to analyze low-level schematic of all future blocks.

    This model would be very useful for:

    • Understand upcoming amount of work;
    • Count required number of logic elements with different types
    • Implement and do debugging the circuit of logic sequencer.
    • Analyze performance issues, and find ways to get maximum performance.

    During the first time, while no DekatronPC blocks are exit, I will use FPGA emulator to analyze correctness.

    While new computer blocks will be done, I will replace emulated parts with the physical one - So just right after the first computer block become to real life - I'll already can show how it works.

    Now, I'm working on instruction fetching, and loop handling code. All the code is available on the github repository

  • Vacuum tube test board №1. Circuits

    Artem Kashkanov04/08/2020 at 08:04 0 comments

    I'm done with soldering and testing test board №1.

    Logic elements:

    2OR, 2OR-NOT, Two rising-front Single-pulse circuits and High-level to low-level logic ranges converter.

    Circuits. 


  • I Started assembly of vacuum tube logic test board

    Artem Kashkanov04/07/2020 at 07:54 0 comments

    Two schemes from IBM 650 manual - 2OR and 2OR-NOT. Stay tuned for more information about each circuit.

  • The most insane terminal for lamp computer

    Artem Kashkanov10/25/2019 at 07:21 0 comments

    I received the most insane terminal for DekatronPC project. This is vector display RIN-609 with keyboard, which was used as a I/O-terminal for soviet BESM-6  and M-400 computers. Can be used instead of Videoton-340.

    Mine variant goes with ferrite core memory RAM module, but next generation of this device were produces with static RAM already.

  • 9-track tape recorder. Tape loading test

    Artem Kashkanov06/15/2019 at 18:17 0 comments

    I tried to turn On one of two tape recorders and tried to load tape. So, it's work. Next stage is to check playing and recording modes and try to save and load data to tape.

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Discussions

Ken Yap wrote 06/16/2019 at 11:47 point

Cool! Dekatrons, I remember those. Counter and display in the same tube. What's not to like? 👍

  Are you sure? yes | no

Dave's Dev Lab wrote 04/16/2018 at 22:14 point

Hey Artem! the witch document you have is a very old version, i have an updated one with new graphics and corrections - https://github.com/prpplague/witch_dev/blob/master/documentation/harwell-ee-1951-txt.pdf

also, all of the WITCH documentation i have can be found in my github including recreated drawings: 

https://github.com/prpplague/witch_dev/tree/master/documentation

  Are you sure? yes | no

Artem Kashkanov wrote 04/21/2018 at 07:39 point

Wow! Thanks for clearing the document!

  Are you sure? yes | no

roelh wrote 02/03/2018 at 18:34 point

Hi Artem,

sounds like a nice project !

In your title you talk about 'other cold cathode tubes' , so I think you will like the clock with neon tube counters made by a Dutch guy:

http://www.pa3fwm.nl/projects/neonclock/

I don't know how may decatrons you have, but instead of a brainf*ck computer you could perhaps build a more 'real' computer like the witch (that you will know):

https://hackaday.io/project/19955-witch-e-decimal-based-computer

But you could build a version with real decatrons instead of chip counters. You could be the first one to build a computer or calculator without transistors or chips (tubes only).

The witch uses decatrons (quite a lot) for the main memory. If you plan to use ferrite memory,  you will need the decatrons and other tubes just for control functions, and then the 30 that I see on your picture might be enough.

The 'real' computer, as I see it, will only have move, increment and decrement functions. But you will need several pointers to memory, and a displacement in the instruction, to create a indirect-with-displacement addressing mode that will lead to an efficient processor. Increment and decrement can be done by your decatrons. In another implementation, increment and decrement would only need a shift and an XOR gate, to count in a LFSR sequence. 

Your 'real' computer could demonstrate arithmetic and trig/log calculations, as well as playing Tetris or other fun stuff.

  Are you sure? yes | no

Artem Kashkanov wrote 02/03/2018 at 20:37 point

Thanks for your advices! 

I know about Dutch guy clock - I thought to build the same one using MTX-90 tiratrons, but why to create yet another clock... 

Currently I have 25 dekatrons - USSR models: A101, A102, A103 It might be enough to build architerture like BfPC - with three bi-directional counters - IP counter, AP counter and Data value counter.  

Anyway I have no idea how this project will look like, just assume the same arch as my current project, but you noticed right thing - this would be silicon-less device.

Mandatory requirement - tubes only (with some few relays).  

  Are you sure? yes | no

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